Test0 Microcode
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System Microcode

This page is actually the source code for the M-1 microcode to be used in the microcode-level simulator, as well as the actual bits to be burned into the proms.  It is processed by extracting the text and processing with cpp and a Perl script (see the Software page for more details).  The created files are:

bulletmcode.h - Description of the fields within the microinstruction word.
bulletmcode.c - An initialized array representing the microcode image.
bulletmcdefs.h - #defines for microcode fields.
bulletprombits.h - The initialization declaration for the 512 56-bit microinstruction words.
bulletprom0.hex .. prom4.hex - Hex images of the slices of the microcode store to be fed into the PROM programmer.
bulletopcodes.h - Opcode strings.
//=====================================================
// BEGIN mcode.h
/* Define for micro instruction word.  Assume I'll be using 512x8 bipolar
 * PROMs.  This version is quite a bit more compact than previous ones,
 * but at the cost of having addition field decoding logic.  Initial plan
 * is to send these signals across the backplane and do decoding on the
 * appropriate card.
 *
 * Note that the encoding here is getting pretty ugly.  I'm trying hard to
 * keep the microcode store down to 5 PROMS - 16 bits for enable signals, 
 * 16 bits for latch signals and 8 bits for the next field. 
 */
typedef struct {
	unsigned next:8;	// Next micro-op to exec. 0x00 means
				// use output of priority encoder, 0xff
				// means use IR[0..7].  Also a significant
				// bit of !(IR[0..7]==0xff) to give the full
				// 9-bit microcode address.
	unsigned latch:4;	// Register latch signal. Value:
				// 0x0 : none
				// 0x1 : MSW (flag nibble only, from Z)
				// 0x2 : C
				// 0x3 : PC
				// 0x4 : DP
				// 0x5 : SP
				// 0x6 : A
				// 0x7 : B
				// 0x8 : MDR (from Z)
				// 0x9 : PTB
				// 0xa : [A low placeholder]
				// 0xb : [A high placeholder]
				// 0xc : [B low placeholder]
				// 0xd : [C low placeholder]
				// 0xe : [SSP placeholder]
				// 0xf : IR_REG (IR[5..7])
	unsigned lmar:1;	// Latch MAR
	unsigned lmdrlo:1;	// Latch MDR(lo) from dbus
	unsigned lmdrhi:1;	// Latch MDR(hi) from dbus
	unsigned emdrlo:1;	// Drive dbus with MDR(lo)
	unsigned emdrhi:1;	// Drive dbus with MDR(hi)
	unsigned priv:1;	// Priviliged instruction
	unsigned lmode:1;	// Latch (M)ode bit in MSW
	unsigned lpaging:1;	// Latch (P)aging enable bit in MSW
	unsigned misc:4;	// Controls signals which never occur at the
				// same time:
				// 0x0 : none
				// 0x1 : 
				// 0x2 : halt
				// 0x3 : 
				// 0x4 : trap on overflow
				// 0x5 : latch PTE
				// 0x6 : set flags (from alu op)
				// 0x7 : init_inst (clear MDR, PC->TPC, latch IR)
				// 0x8 : right shift alu output
				// 0x9 : DMA acknowledge
				// 0xa : latch MSW[ie] (Interrupt Enable)
				// 0xb : do branch
				// 0xc : latch MSW[in_trap]
				// 0xd : commit state
				// 0xe : 
				// 0xf : 
	unsigned e_l:4;		// Enable L bus
				// 0x0 : MAR
				// 0x1 : MSW
				// 0x2 : C
				// 0x3 : PC
				// 0x4 : DP
				// 0x5 : SP
				// 0x6 : A
				// 0x7 : B
				// 0x8 : MDR
				// 0x9 : PTB
				// 0xa : SSP
				// 0xb : TPC
				// 0xc : 
				// 0xd : 
				// 0xe :
				// 0xf : IR_BASE (4+IR[6..7])
	unsigned e_r:2;		// Enable R bus
				// 0x0 : MDR
				// 0x1 : Immediate
				// 0x2 : Fault code/encoder
				// 0x3 :
	unsigned immval:2;	// Immediate value
				// 0x0 : 0
				// 0x1 : 1
				// 0x2 : -2
				// 0x3 : -1
	unsigned aluop_size:1;	// 0x0 -> 16 bits, 0x1 -> 8 bits
	unsigned aluop:2;	// Which alu operation to perform
				// 0x0 : IR[1..3]
				// 0x1 : AND
				// 0x2 : SUB
				// 0x3 : ADD
	unsigned carry:1;	// 0x0 -> 0, 0x1 -> MSW[c]
	unsigned l_size:1;	// 0x0 -> latch byte, 0x1 -> latch word
	unsigned br_sense:1;	// 0x0 -> don't negate, 0x1 -> negate
				// Non-negated branch conditions are:
				// 	0x0 : eq
				// 	0x1 : eq
				// 	0x2 : lt
				// 	0x3 : le
				// 	0x4 : ltu
				// 	0x5 : leu
				// 	0x6 : eq
				// 	0x7 : ne
	unsigned user_ptb:1;	// User page table base override
	unsigned code_ptb:1;	// 0 to select data region of PTB, 1 for code
} mcode_rec_t;
extern mcode_rec_t mcode_store[512];
// END mcode.h
//=====================================================
// BEGIN mcode.c
//
#include "mcode.h"
mcode_rec_t mcode_store[512] = {
#include "prombits.h"
};
// END mcode.c
//=====================================================
// PREPROCESS prombits.h
// BEGIN mcdefs.h
// Register defines for LATCH() and EL() 
#define	R_MSW	1
#define	R_C	2
#define	R_PC	3
#define	R_DP	4
#define	R_SP	5
#define	R_A	6
#define	R_B	7
#define	R_MDR	8
#define	R_PTB	9
#define	R_SSP	10
// Register defines for LATCH()-only
#define	R_NONE	0
#define	R_IR_REG	15
// Register defines for EL()-only
#define	R_MAR	0
#define	R_TPC	11
#define R_FCODE	12
#define	R_IR_BASE	15
// Register defines for ER()
#define	ER_MDR	0
#define	ER_IMM	1
#define	ER_FAULT	2
// Defines for IMMVAL()
#define	IMM_0	0
#define	IMM_1	1
#define	IMM_NEG1	3
#define	IMM_NEG2	2
// Defines for MISC()
#define	M_NONE	0
#define M_SYSCALL 1
#define	M_HALT	2
#define M_BKPT 3
#define	M_TRAPO	4
#define	M_LPTE	5
#define	M_SET_FLAGS	6
#define	M_INIT_INST	7
#define	M_RSHIFT	8
#define	M_DMA_ACK	9
#define	M_LEI	10
#define	M_DO_BRANCH	11
#define M_CLR_TRAP	12
#define M_COMMIT 13
// Defines for ALUOP(op,size,carry)
#define	OP_IR13	0
#define	OP_AND	1
#define	OP_SUB	2
#define	OP_ADD	3
#define	WORD	0
#define	BYTE	1
#define	LWORD	1
#define	LBYTE	0
#define	NO_CARRY	0
#define	CARRY_IN	1
// Defines for CBR()
#define	B_NORMAL	0
#define	B_NEGATED	1
// END mcdefs.h
#define NEXT_POS	 0
#define LATCH_POS	 1
#define LMAR_POS	 2
#define LMDRLO_POS	 3
#define LMDRHI_POS	 4
#define EMDRLO_POS	 5
#define EMDRHI_POS	 6
#define PRIV_POS	 7
#define LMODE_POS	 8
#define LPAGING_POS	 9
#define MISC_POS	 10
#define E_L_POS		 11
#define E_R_POS		 12
#define IMMVAL_POS	 13
#define ALUOP_SIZE_POS	 14
#define ALUOP_POS	 15
#define CARRY_POS	 16
#define L_SIZE_POS	 17
#define BR_SENSE_POS	 18
#define USER_PTB_POS	 19
#define CODE_PTB_POS	 20
#define NEXT(VAL)	INIT(NEXT_POS,VAL)
#define LATCH(VAL)	INIT(LATCH_POS,VAL)
#define LMAR(VAL)	INIT(LMAR_POS,VAL)
#define LMDRLO(VAL)	INIT(LMDRLO_POS,VAL)
#define LMDRHI(VAL)	INIT(LMDRHI_POS,VAL)
#define EMDRLO(VAL)	INIT(EMDRLO_POS,VAL)
#define EMDRHI(VAL)	INIT(EMDRHI_POS,VAL)
#define PRIV(VAL)	INIT(PRIV_POS,VAL)
#define LMODE(VAL)	INIT(LMODE_POS,VAL)
#define LPAGING(VAL)	INIT(LPAGING_POS,VAL)
#define MISC(VAL)	INIT(MISC_POS,VAL)
#define E_L(VAL)	INIT(E_L_POS,VAL)
#define E_R(VAL)	INIT(E_R_POS,VAL)
#define IMMVAL(VAL)	INIT(IMMVAL_POS,VAL)
#define ALUOP_SIZE(VAL)	INIT(ALUOP_SIZE_POS,VAL)
#define ALUOP(VAL)	INIT(ALUOP_POS,VAL)
#define CARRY(VAL)	INIT(CARRY_POS,VAL)
#define L_SIZE(VAL)	INIT(L_SIZE_POS,VAL)
#define BR_SENSE(VAL)	INIT(BR_SENSE_POS,VAL)
#define USER_PTB(VAL)	INIT(USER_PTB_POS,VAL)
#define CODE_PTB(VAL)	INIT(CODE_PTB_POS,VAL)
#define CBR(SENSE,TGT)	MISC(M_DO_BRANCH),BR_SENSE(SENSE),NEXT(TGT)
#define L(REG,SIZE)	LATCH(REG),L_SIZE(SIZE)
#define	USE_IR	0xff
#define READLO LMDRLO(1)
#define READHI LMDRHI(1)
#define READEXT LMDRLO(1),LMDRHI(1)
#define WRITELO EMDRLO(1)
#define WRITEHI EMDRHI(1)
#define	INC_TO_Z(REG) E_L(REG),E_R(ER_IMM),IMMVAL(IMM_1),ALU(OP_ADD,WORD,NO_CARRY)
#define INC2_TO_Z(REG) E_L(REG),E_R(ER_IMM),IMMVAL(IMM_NEG2),ALU(OP_SUB,WORD,NO_CARRY)
#define	DEC_TO_Z(REG) E_L(REG),E_R(ER_IMM),IMMVAL(IMM_NEG1),ALU(OP_ADD,WORD,NO_CARRY)
#define	ZERO_TO_Z E_L(R_MDR),E_R(ER_IMM),IMMVAL(IMM_0),ALU(OP_AND,WORD,NO_CARRY)
#define NEG1_TO_Z E_L(R_MDR),E_R(ER_IMM),IMMVAL(IMM_NEG1),ALU(OP_ADD,WORD,NO_CARRY)
#define TO_Z(REG) E_L(REG),E_R(ER_IMM),IMMVAL(IMM_NEG1),ALU(OP_AND,WORD,NO_CARRY)
#define TO_Z8(REG) E_L(REG),E_R(ER_IMM),IMMVAL(IMM_NEG1),ALU(OP_AND,BYTE,NO_CARRY)
#define	LDHI READHI,INC_TO_Z(R_MAR),LMAR(1)
#define LDLO READLO,TO_Z(R_PC),LMAR(1) 
#define STHI WRITEHI,INC_TO_Z(R_MAR),LMAR(1)
#define STLO WRITELO,TO_Z(R_PC),LMAR(1)
#define LDIMMHI CODE_PTB(1),READHI,L(R_PC,LWORD),INC_TO_Z(R_PC),LMAR(1)
#define LDIMMLO CODE_PTB(1),READLO,L(R_PC,LWORD),INC_TO_Z(R_PC),LMAR(1)
#define LDIMMEXT CODE_PTB(1),READEXT,L(R_PC,LWORD),INC_TO_Z(R_PC),LMAR(1)
#define GEN_ADDR(BASE) E_L(BASE),E_R(ER_MDR),ALU(OP_ADD,WORD,NO_CARRY)
#define COMPARE_0(REG) E_L(REG),E_R(ER_IMM),IMMVAL(IMM_0),ALU(OP_SUB,WORD,NO_CARRY)
#define ALU(OP,SZ,CRY) ALUOP(OP),ALUOP_SIZE(SZ),CARRY(CRY)
#define FETCH_OP CODE_PTB(1),READLO,MISC(M_INIT_INST),INC_TO_Z(R_MAR),L(R_PC,LWORD),LMAR(1),NEXT(UNUSABLE)

Bottom half of PROM -  (starting point of each instruction, using opcode as direct index)

0x00 halt ; NEXT(LeaPC)
0x01 ld.8 A,#u16(SP) ; NEXT(LeaPC)
0x02 push C ; NEXT(LeaPC)
0x03 push PC ; NEXT(LeaPC)
0x04 push DP ; NEXT(LeaPC)
0x05 ld.8 B,#u16(SP) ; NEXT(LeaPC)
0x06 push A ; NEXT(LeaPC)
0x07 push B ; NEXT(LeaPC)
0x08 br.ne #d16 ; NEXT(LeaPC)
0x09 pop MSW ; NEXT(LeaPC)
0x0a pop C ; NEXT(LeaPC)
0x0b pop PC ; NEXT(LeaPC)
0x0c pop DP ; NEXT(LeaPC)
0x0d pop SP ; NEXT(LeaPC)
0x0e pop A ; NEXT(LeaPC)
0x0f pop B ; NEXT(LeaPC)
0x10 ld.8 A,#u16(DP) ; NEXT(LeaPC)
0x11 ld.8 A,#u8(SP) ; NEXT(LeaPC)
0x12 ld.8 A,#u8(A) ; NEXT(LeaPC)
0x13 ld.8 A,#u8(B) ; NEXT(LeaPC)
0x14 ld.8 B,#u16(DP) ; NEXT(LeaPC)
0x15 ld.8 B,#u8(SP) ; NEXT(LeaPC)
0x16 ld.8 B,#u8(A) ; NEXT(LeaPC)
0x17 ld.8 B,#u8(B) ; NEXT(LeaPC)
0x18 ld.16 A,#u16(DP) ; NEXT(LeaPC)
0x19 ld.16 A,#u8(SP) ; NEXT(LeaPC)
0x1a ld.16 A,#u8(A) ; NEXT(LeaPC)
0x1b ld.16 A,#u8(B) ; NEXT(LeaPC)
0x1c ld.16 B,#u16(DP) ; NEXT(LeaPC)
0x1d ld.16 B,#u8(SP) ; NEXT(LeaPC)
0x1e ld.16 B,#u8(A) ; NEXT(LeaPC)
0x1f ld.16 B,#u8(B) ; NEXT(LeaPC)
0x20 sub.8 A,#u16(DP) ; NEXT(LeaPC)
0x21 sub.8 A,#u8(SP) ; NEXT(LeaPC)
0x22 push MSW ; NEXT(LeaPC)
0x23 sub.8 A,#u8(B) ; NEXT(LeaPC)
0x24 sub.8 A,#i8_1 ; NEXT(LeaPC)
0x25 sub.8 A,#1 ; NEXT(LeaPC)
0x26 push SP ; NEXT(LeaPC)
0x27 sub.8 A,B ; NEXT(LeaPC)
0x28 sub.16 A,#u16(DP) ; NEXT(LeaPC)
0x29 sub.16 A,#u8(SP) ; NEXT(LeaPC)
0x2a nop0 ; NEXT(LeaPC)
0x2b sub.16 A,#u8(B) ; NEXT(LeaPC)
0x2c sub.16 A,#i16_exti8 ; NEXT(LeaPC)
0x2d sub.16 A,#exti8 ; NEXT(LeaPC)
0x2e wcpte A,(B) ; NEXT(LeaPC)
0x2f sub.16 A,B ; NEXT(LeaPC)
0x30 add.8 A,#u16(DP) ; NEXT(LeaPC)
0x31 add.8 A,#u8(SP) ; NEXT(LeaPC)
0x32 br A ; NEXT(LeaPC)
0x33 add.8 A,#u8(B) ; NEXT(LeaPC)
0x34 add.8 A,#i8_1 ; NEXT(LeaPC)
0x35 add.8 A,#1 ; NEXT(LeaPC)
0x36 add.8 A,A ; NEXT(LeaPC)
0x37 add.8 A,B ; NEXT(LeaPC)
0x38 add.16 A,#u16(DP) ; NEXT(LeaPC)
0x39 add.16 A,#u8(SP) ; NEXT(LeaPC)
0x3a syscall #sys_num8 ; NEXT(LeaPC)
0x3b add.16 A,#u8(B) ; NEXT(LeaPC)
0x3c add.16 A,#i16_exti8 ; NEXT(LeaPC)
0x3d add.16 A,#exti8 ; NEXT(LeaPC)
0x3e add.16 A,A ; NEXT(LeaPC)
0x3f add.16 A,B ; NEXT(LeaPC)
0x40 cmp.8 A,#u16(DP) ; NEXT(LeaPC)
0x41 cmp.8 A,#u8(SP) ; NEXT(LeaPC)
0x42 nop1 ; NEXT(LeaPC)
0x43 cmp.8 A,#u8(B) ; NEXT(LeaPC)
0x44 cmp.8 A,#i8_0 ; NEXT(LeaPC)
0x45 cmp.8 A,#0 ; NEXT(LeaPC)
0x46 xor.16 A,A ; NEXT(LeaPC)
0x47 cmp.8 A,B ; NEXT(LeaPC)
0x48 cmp.16 A,#u16(DP) ; NEXT(LeaPC)
0x49 cmp.16 A,#u8(SP) ; NEXT(LeaPC)
0x4a nop2 ; NEXT(LeaPC)
0x4b cmp.16 A,#u8(B) ; NEXT(LeaPC)
0x4c cmp.16 A,#i16_exti8_0 ; NEXT(LeaPC)
0x4d cmp.16 A,#exti8_0 ; NEXT(LeaPC)
0x4e cmp.16 A,#0 ; NEXT(LeaPC)
0x4f cmp.16 A,B ; NEXT(LeaPC)
0x50 or.8 A,#u16(DP) ; NEXT(LeaPC)
0x51 or.8 A,#u8(SP) ; NEXT(LeaPC)
0x52 nop3 ; NEXT(LeaPC)
0x53 or.8 A,#u8(B) ; NEXT(LeaPC)
0x54 or.8 A,#i8_1 ; NEXT(LeaPC)
0x55 or.8 A,#1 ; NEXT(LeaPC)
0x56 br.leu #d16 ; NEXT(LeaPC)
0x57 or.8 A,B ; NEXT(LeaPC)
0x58 or.16 A,#u16(DP) ; NEXT(LeaPC)
0x59 or.16 A,#u8(SP) ; NEXT(LeaPC)
0x5a nop8 ; NEXT(LeaPC)
0x5b or.16 A,#u8(B) ; NEXT(LeaPC)
0x5c or.16 A,#i16_exti8 ; NEXT(LeaPC)
0x5d or.16 A,#exti8 ; NEXT(LeaPC)
0x5e br.gtu #d16 ; NEXT(LeaPC)
0x5f or.16 A,B ; NEXT(LeaPC)
0x60 and.8 A,#u16(DP) ; NEXT(LeaPC)
0x61 and.8 A,#u8(SP) ; NEXT(LeaPC)
0x62 nop4 ; NEXT(LeaPC)
0x63 and.8 A,#u8(B) ; NEXT(LeaPC)
0x64 and.8 A,#i8_1 ; NEXT(LeaPC)
0x65 and.8 A,#1 ; NEXT(LeaPC)
0x66 sex A ; NEXT(LeaPC)
0x67 and.8 A,B ; NEXT(LeaPC)
0x68 and.16 A,#u16(DP) ; NEXT(LeaPC)
0x69 and.16 A,#u8(SP) ; NEXT(LeaPC)
0x6a nop5 ; NEXT(LeaPC)
0x6b and.16 A,#u8(B) ; NEXT(LeaPC)
0x6c and.16 A,#i16_exti8 ; NEXT(LeaPC)
0x6d and.16 A,#exti8 ; NEXT(LeaPC)
0x6e sex B ; NEXT(LeaPC)
0x6f and.16 A,B ; NEXT(LeaPC)
0x70 lea A,#u16(DP) ; NEXT(LeaPC)
0x71 lea A,#u16(SP) ; NEXT(LeaPC)
0x72 lea A,#u16(A) ; NEXT(LeaPC)
0x73 lea A,#u16(B) ; NEXT(LeaPC)
0x74 lea B,#u16(DP) ; NEXT(LeaPC)
0x75 lea B,#u16(SP) ; NEXT(LeaPC)
0x76 lea B,#u16(A) ; NEXT(LeaPC)
0x77 lea B,#u16(B) ; NEXT(LeaPC)
0x78 ld.8 A,#u8 ; NEXT(LeaPC)
0x79 ld.8 B,#u8 ; NEXT(LeaPC)
0x7a ld.16 A,#exti8_u16 ; NEXT(LeaPC)
0x7b ld.16 B,#exti8_u16 ; NEXT(LeaPC)
0x7c ld.16 A,#u16 ; NEXT(LeaPC)
0x7d ld.16 B,#u16 ; NEXT(LeaPC)
0x7e adc.16 A,A ; NEXT(LeaPC)
0x7f adc.16 A,B ; NEXT(LeaPC)
0x80 call #d16 ; NEXT(LeaPC)
0x81 ld.16 A,#u16(SP) ; NEXT(LeaPC)
0x82 call A ; NEXT(LeaPC)
0x83 br #d16_d8 ; NEXT(LeaPC)
0x84 sbr #d8 ; NEXT(LeaPC)
0x85 ld.16 B,#u16(SP) ; NEXT(LeaPC)
0x86 lea A,#u16(PC) ; NEXT(LeaPC)
0x87 lea B,#u16(PC) ; NEXT(LeaPC)
0x88 copy A,MSW ; NEXT(LeaPC)
0x89 br.eq #d16 ; NEXT(LeaPC)
0x8a reti ; NEXT(LeaPC)
0x8b trapo ; NEXT(LeaPC)
0x8c bset.8 A,#mask8,#d8 ; NEXT(LeaPC)
0x8d bclr.8 A,#mask8,#d8 ; NEXT(LeaPC)
0x8e bset.16 A,#mask16,#d8 ; NEXT(LeaPC)
0x8f bclr.16 A,#mask16,#d8 ; NEXT(LeaPC)
0x90 cmpb.eq.8 A,#u16(DP),#d8 ; NEXT(LeaPC)
0x91 cmpb.eq.8 A,#u8(SP),#d8 ; NEXT(LeaPC)
0x92 copy B,A ; NEXT(LeaPC)
0x93 cmpb.eq.8 A,#u8(B),#d8 ; NEXT(LeaPC)
0x94 cmpb.eq.8 A,#i8_0,#d8 ; NEXT(LeaPC)
0x95 cmpb.eq.8 A,#0,#d8 ; NEXT(LeaPC)
0x96 copy C,A ; NEXT(LeaPC)
0x97 cmpb.eq.8 A,B,#d8 ; NEXT(LeaPC)
0x98 cmpb.eq.16 A,#u16(DP),#d8 ; NEXT(LeaPC)
0x99 cmpb.eq.16 A,#u8(SP),#d8 ; NEXT(LeaPC)
0x9a copy A,B ; NEXT(LeaPC)
0x9b cmpb.eq.16 A,#u8(B),#d8 ; NEXT(LeaPC)
0x9c cmpb.eq.16 A,#i16_exti8_0,#d8 ; NEXT(LeaPC)
0x9d cmpb.eq.16 A,#exti8_0,#d8 ; NEXT(LeaPC)
0x9e cmpb.eq.16 A,#0,#d8 ; NEXT(LeaPC)
0x9f cmpb.eq.16 A,B,#d8 ; NEXT(LeaPC)
0xa0 cmpb.lt.8 A,#u16(DP),#d8 ; NEXT(LeaPC)
0xa1 cmpb.lt.8 A,#u8(SP),#d8 ; NEXT(LeaPC)
0xa2 nop6 ; NEXT(LeaPC)
0xa3 cmpb.lt.8 A,#u8(B),#d8 ; NEXT(LeaPC)
0xa4 cmpb.lt.8 A,#i8_0,#d8 ; NEXT(LeaPC)
0xa5 cmpb.lt.8 A,#0,#d8 ; NEXT(LeaPC)
0xa6 br.lt #d16 ; NEXT(LeaPC)
0xa7 cmpb.lt.8 A,B,#d8 ; NEXT(LeaPC)
0xa8 cmpb.lt.16 A,#u16(DP),#d8 ; NEXT(LeaPC)
0xa9 cmpb.lt.16 A,#u8(SP),#d8 ; NEXT(LeaPC)
0xaa nop7 ; NEXT(LeaPC)
0xab cmpb.lt.16 A,#u8(B),#d8 ; NEXT(LeaPC)
0xac cmpb.lt.16 A,#i16_exti8,#d8 ; NEXT(LeaPC)
0xad cmpb.lt.16 A,#exti8,#d8 ; NEXT(LeaPC)
0xae br.ge #d16 ; NEXT(LeaPC)
0xaf cmpb.lt.16 A,B,#d8 ; NEXT(LeaPC)
0xb0 cmpb.le.8 A,#u16(DP),#d8 ; NEXT(LeaPC)
0xb1 cmpb.le.8 A,#u8(SP),#d8 ; NEXT(LeaPC)
0xb2 nop8 ; NEXT(LeaPC)
0xb3 cmpb.le.8 A,#u8(B),#d8 ; NEXT(LeaPC)
0xb4 cmpb.le.8 A,#i8,#d8 ; NEXT(LeaPC)
0xb5 br.le #d16 ; NEXT(LeaPC)
0xb6 copy DP,A ; NEXT(LeaPC)
0xb7 cmpb.le.8 A,B,#d8 ; NEXT(LeaPC)
0xb8 cmpb.le.16 A,#u16(DP),#d8 ; NEXT(LeaPC)
0xb9 cmpb.le.16 A,#u8(SP),#d8 ; NEXT(LeaPC)
0xba copy A,DP ; NEXT(LeaPC)
0xbb cmpb.le.16 A,#u8(B),#d8 ; NEXT(LeaPC)
0xbc cmpb.le.16 A,#i16_exti8,#d8 ; NEXT(LeaPC)
0xbd cmpb.le.16 A,#exti8,#d8 ; NEXT(LeaPC)
0xbe br.gt #d16 ; NEXT(LeaPC)
0xbf cmpb.le.16 A,B,#d8 ; NEXT(LeaPC)
0xc0 br.geu #d16 ; NEXT(LeaPC)
0xc1 st.8 #u16(SP),A ; NEXT(LeaPC)
0xc2 shl.16 A ; NEXT(LeaPC)
0xc3 shr.16 A ; NEXT(LeaPC)
0xc4 shl.16 B ; NEXT(LeaPC)
0xc5 st.8 #u16(SP),B ; NEXT(LeaPC)
0xc6 shr.16 B ; NEXT(LeaPC)
0xc7 xor.16 A,B ; NEXT(LeaPC)
0xc8 copy PTB,A ; NEXT(LeaPC)
0xc9 st.16 #u16(SP),A ; NEXT(LeaPC)
0xca copy MSW,A ; NEXT(LeaPC)
0xcb copy SP,A ; NEXT(LeaPC)
0xcc ld.16 C,#exti8_u16 ; NEXT(LeaPC)
0xcd st.16 #u16(SP),A ; NEXT(LeaPC)
0xce ld.16 C,#u16 ; NEXT(LeaPC)
0xcf br.ltu #d16 ; NEXT(LeaPC)
0xd0 st.8 #u16(DP),A ; NEXT(LeaPC)
0xd1 st.8 #u8(SP),A ; NEXT(LeaPC)
0xd2 st.8 #u8(A),A ; NEXT(LeaPC)
0xd3 st.8 #u8(B),A ; NEXT(LeaPC)
0xd4 st.8 #u16(DP),B ; NEXT(LeaPC)
0xd5 st.8 #u8(SP),B ; NEXT(LeaPC)
0xd6 st.8 #u8(A),B ; NEXT(LeaPC)
0xd7 st.8 #u8(B),B ; NEXT(LeaPC)
0xd8 st.16 #u16(DP),A ; NEXT(LeaPC)
0xd9 st.16 #u8(SP),A ; NEXT(LeaPC)
0xda st.16 #u8(A),A ; NEXT(LeaPC)
0xdb st.16 #u8(B),A ; NEXT(LeaPC)
0xdc st.16 #u16(DP),B ; NEXT(LeaPC)
0xdd st.16 #u8(SP),B ; NEXT(LeaPC)
0xde st.16 #u8(A),B ; NEXT(LeaPC)
0xdf st.16 #u8(B),B ; NEXT(LeaPC)
0xe0 ldcode.8 A,(B) ; NEXT(LeaPC)
0xe1 ldcode.16 A,(B) ; NEXT(LeaPC)
0xe2 stcode.8 (B),A ; NEXT(LeaPC)
0xe3 stcode.16 (B),A ; NEXT(LeaPC)
0xe4 enter #fsize16_8 ; NEXT(LeaPC)
0xe5 enter #fsize8 ; NEXT(LeaPC)
0xe6 vshl.16 A ; NEXT(LeaPC)
0xe7 vshl.16 B ; NEXT(LeaPC)
0xe8 memcopy ; NEXT(LeaPC)
0xe9 tosys ; NEXT(LeaPC)
0xea fromsys ; NEXT(LeaPC)
0xeb ldclr.8 A,(B) ; NEXT(LeaPC)
0xec wdpte A,(B) ; NEXT(LeaPC)
0xed sbc.16 A,B ; NEXT(LeaPC)
0xee vshr.16 A ; NEXT(LeaPC)
0xef vshr.16 B ; NEXT(LeaPC)
0xf0 cmpb.ne.8 A,#u16(DP),#d8 ; NEXT(LeaPC)
0xf1 cmpb.ne.8 A,#u8(SP),#d8 ; NEXT(LeaPC)
0xf2 copy A,C ; NEXT(LeaPC)
0xf3 cmpb.ne.8 A,#u8(B),#d8 ; NEXT(LeaPC)
0xf4 cmpb.ne.8 A,#i8_0,#d8 ; NEXT(LeaPC)
0xf5 cmpb.ne.8 A,#0,#d8 ; NEXT(LeaPC)
0xf6 copy A,SP ; NEXT(LeaPC)
0xf7 cmpb.ne.8 A,B,#d8 ; NEXT(LeaPC)
0xf8 cmpb.ne.16 A,#u16(DP),#d8 ; NEXT(LeaPC)
0xf9 cmpb.ne.16 A,#u8(SP),#d8 ; NEXT(LeaPC)
0xfa bkpt ; NEXT(LeaPC)
0xfb cmpb.ne.16 A,#u8(B),#d8 ; NEXT(LeaPC)
0xfc cmpb.ne.16 A,#i16_exti8_0,#d8 ; NEXT(LeaPC)
0xfd cmpb.ne.16 A,#exti8_0,#d8 ; NEXT(LeaPC)
0xfe cmpb.ne.16 A,#0,#d8 ; NEXT(LeaPC)
0xff cmpb.ne.16 A,B,#d8 ; NEXT(LeaPC)

Top half of PROM - continuation microcode.

0x100 Fetch ; NEXT(FALLTHRU)
0x101 IRQ5 ; NEXT(FALLTHRU)
0x102 IRQ4 ; NEXT(FALLTHRU)
0x103 IRQ3 ; NEXT(FALLTHRU)
0x104 IRQ2 ; NEXT(FALLTHRU)
0x105 IRQ1 ; NEXT(FALLTHRU)
0x106 IRQ0 ; NEXT(FALLTHRU)
0x107 DMA_req ; NEXT(FALLTHRU)
0x108 Fault_syscall ; NEXT(FALLTHRU)
0x109 ; NEXT(FALLTHRU)
0x10a Fault_ovflo ; NEXT(FALLTHRU)
0x10b Fault_priv ; NEXT(FALLTHRU)
0x10c Fault_bkpt ; NEXT(FALLTHRU)
0x10d Fault_nw ; NEXT(FALLTHRU)
0x10e Fault_np ; NEXT(FALLTHRU)
0x10f ; NEXT(FALLTHRU)
0x110 Aluop8_indir ; NEXT(Aluop8)
0x111 ; NEXT(Error)
0x112 Aluop8 ; NEXT(Aluop16_indir)
0x113 Aluop8_indir16 ; NEXT(Error)
0x114 Aluop16_indir ; NEXT(Cmp16)
0x115 ; NEXT(Error)
0x116 ; NEXT(Error)
0x117 Aluop16 ; NEXT(Error)
0x118 Aluop16_indir16 ; NEXT(Error)
0x119 Cmp8_indir ; NEXT(Error)
0x11a ; NEXT(Error)
0x11b Cmp8 ; NEXT(Cmpb8_indir)
0x11c Cmp8_indir16 ; NEXT(Error)
0x11d Cmp16_indir ; NEXT(Error)
0x11e ; NEXT(Error)
0x11f ; NEXT(Error)
0x120 Cmp16 ; NEXT(Cmp8)
0x121 Cmp16_indir16 ; NEXT(FALLTHRU)
0x122 Cmpb8_indir ; NEXT(FALLTHRU)
0x123 ; NEXT(FALLTHRU)
0x124 Cmpb8 ; NEXT(FALLTHRU)
0x125 Cmpb8_indir16 ; NEXT(FALLTHRU)
0x126 Cmpb16_indir ; NEXT(FALLTHRU)
0x127 ; NEXT(FALLTHRU)
0x128 ; NEXT(FALLTHRU)
0x129 Cmpb16 ; NEXT(FALLTHRU)
0x12a Cmpb16_indir16 ; NEXT(FALLTHRU)
0x12b CheckBr ; NEXT(FALLTHRU)
0x12c TakenBr ; NEXT(FALLTHRU)
0x12d BrNormal ; NEXT(FALLTHRU)
0x12e BrNegated ; NEXT(FALLTHRU)
0x12f Bset8 ; NEXT(FALLTHRU)
0x130 CheckBrNeg ; NEXT(FALLTHRU)
0x131 Bclr8 ; NEXT(FALLTHRU)
0x132 Bset16 ; NEXT(FALLTHRU)
0x133 ; NEXT(FALLTHRU)
0x134 Bclr16 ; NEXT(FALLTHRU)
0x135 ; NEXT(FALLTHRU)
0x136 Push16 ; NEXT(FALLTHRU)
0x137 ; NEXT(FALLTHRU)
0x138 ; NEXT(FALLTHRU)
0x139 Pop16 ; NEXT(FALLTHRU)
0x13a ; NEXT(FALLTHRU)
0x13b ; NEXT(FALLTHRU)
0x13c ; NEXT(FALLTHRU)
0x13d Lda8_8 ; NEXT(FALLTHRU)
0x13e ; NEXT(FALLTHRU)
0x13f ; NEXT(FALLTHRU)
0x140 Lda8_16 ; NEXT(FALLTHRU)
0x141 Ldb8_8 ; NEXT(FALLTHRU)
0x142 ; NEXT(FALLTHRU)
0x143 ; NEXT(FALLTHRU)
0x144 Ldb8_16 ; NEXT(FALLTHRU)
0x145 Lda16_8 ; NEXT(FALLTHRU)
0x146 ; NEXT(FALLTHRU)
0x147 ; NEXT(FALLTHRU)
0x148 ; NEXT(FALLTHRU)
0x149 Lda16_16 ; NEXT(FALLTHRU)
0x14a Ldb16_8 ; NEXT(FALLTHRU)
0x14b ; NEXT(FALLTHRU)
0x14c ; NEXT(FALLTHRU)
0x14d ; NEXT(FALLTHRU)
0x14e Ldb16_16 ; NEXT(FALLTHRU)
0x14f Sta8_8 ; NEXT(FALLTHRU)
0x150 ; NEXT(FALLTHRU)
0x151 StaLo ; NEXT(FALLTHRU)
0x152 Sta8_16 ; NEXT(FALLTHRU)
0x153 Sta16_8 ; NEXT(FALLTHRU)
0x154 ; NEXT(FALLTHRU)
0x155 ; NEXT(FALLTHRU)
0x156 Sta16_16 ; NEXT(FALLTHRU)
0x157 Stb8_8 ; NEXT(FALLTHRU)
0x158 ; NEXT(FALLTHRU)
0x159 StbLo ; NEXT(FALLTHRU)
0x15a Stb8_16 ; NEXT(FALLTHRU)
0x15b Stb16_8 ; NEXT(FALLTHRU)
0x15c ; NEXT(FALLTHRU)
0x15d ; NEXT(FALLTHRU)
0x15e Stb16_16 ; NEXT(FALLTHRU)
0x15f Sbc16 ; NEXT(FALLTHRU)
0x160 Adc16 ; NEXT(FALLTHRU)
0x161 LdaA_16 ; NEXT(FALLTHRU)
0x162 LdaA ; NEXT(FALLTHRU)
0x163 LdaB_16 ; NEXT(FALLTHRU)
0x164 LdaB ; NEXT(FALLTHRU)
0x165 LdiA8 ; NEXT(FALLTHRU)
0x166 LdiB8 ; NEXT(FALLTHRU)
0x167 LdiA16_lo ; NEXT(FALLTHRU)
0x168 LdiA16 ; NEXT(FALLTHRU)
0x169 LdiB16_lo ; NEXT(FALLTHRU)
0x16a LdiB16 ; NEXT(FALLTHRU)
0x16b LdiC16_lo ; NEXT(FALLTHRU)
0x16c LdiC16 ; NEXT(FALLTHRU)
0x16d RelBrLo ; NEXT(FALLTHRU)
0x16e RelBr ; NEXT(FALLTHRU)
0x16f CallImm ; NEXT(FALLTHRU)
0x170 ; NEXT(FALLTHRU)
0x171 ; NEXT(FALLTHRU)
0x172 ; NEXT(FALLTHRU)
0x173 ; NEXT(FALLTHRU)
0x174 ; NEXT(FALLTHRU)
0x175 CallA ; NEXT(FALLTHRU)
0x176 ; NEXT(FALLTHRU)
0x177 ; NEXT(FALLTHRU)
0x178 LdClr ; NEXT(FALLTHRU)
0x179 ; NEXT(FALLTHRU)
0x17a ; NEXT(FALLTHRU)
0x17b Wcpte ; NEXT(FALLTHRU)
0x17c Enter ; NEXT(FALLTHRU)
0x17d ; NEXT(FALLTHRU)
0x17e ; NEXT(FALLTHRU)
0x17f ; NEXT(FALLTHRU)
0x180 ; NEXT(FALLTHRU)
0x181 ; NEXT(FALLTHRU)
0x182 ; NEXT(FALLTHRU)
0x183 Bcopy ; NEXT(FALLTHRU)
0x184 ; NEXT(FALLTHRU)
0x185 ; NEXT(FALLTHRU)
0x186 ToSys ; NEXT(FALLTHRU)
0x187 ; NEXT(FALLTHRU)
0x188 ; NEXT(FALLTHRU)
0x189 Bcopy0 ; NEXT(FALLTHRU)
0x18a ; NEXT(FALLTHRU)
0x18b Bcopy1 ; NEXT(FALLTHRU)
0x18c   ; NEXT(FALLTHRU)
0x18d FromSys ; NEXT(FALLTHRU)
0x18e ; NEXT(FALLTHRU)
0x18f ; NEXT(FALLTHRU)
0x190 ; NEXT(FALLTHRU)
0x191 ; NEXT(FALLTHRU)
0x192 Fault ; NEXT(FALLTHRU)
0x193 ; NEXT(FALLTHRU)
0x194 ; NEXT(FALLTHRU)
0x195 ; NEXT(FALLTHRU)
0x196 ; NEXT(FALLTHRU)
0x197 ; NEXT(FALLTHRU)
0x198 ; NEXT(FALLTHRU)
0x199 ; NEXT(FALLTHRU)
0x19a ; NEXT(FALLTHRU)
0x19b ; NEXT(FALLTHRU)
0x19c ; NEXT(FALLTHRU)
0x19d ; NEXT(FALLTHRU)
0x19e ; NEXT(FALLTHRU)
0x19f ; NEXT(FALLTHRU)
0x1a0 ; NEXT(FALLTHRU)
0x1a1 ; NEXT(FALLTHRU)
0x1a2 ; NEXT(FALLTHRU)
0x1a3 ; NEXT(FALLTHRU)
0x1a4 ; NEXT(FALLTHRU)
0x1a5 ; NEXT(FALLTHRU)
0x1a6 ; NEXT(FALLTHRU)
0x1a7 ; NEXT(FALLTHRU)
0x1a8 ; NEXT(FALLTHRU)
0x1a9 ; NEXT(FALLTHRU)
0x1aa ; NEXT(FALLTHRU)
0x1ab ; NEXT(FALLTHRU)
0x1ac ; NEXT(FALLTHRU)
0x1ad Reti ; NEXT(FALLTHRU)
0x1ae ; NEXT(FALLTHRU)
0x1af ; NEXT(FALLTHRU)
0x1b0 ; NEXT(FALLTHRU)
0x1b1 ; NEXT(FALLTHRU)
0x1b2 ; NEXT(FALLTHRU)
0x1b3 ; NEXT(FALLTHRU)
0x1b4 ; NEXT(FALLTHRU)
0x1b5 ; NEXT(FALLTHRU)
0x1b6 ; NEXT(FALLTHRU)
0x1b7 ; NEXT(FALLTHRU)
0x1b8 ; NEXT(FALLTHRU)
0x1b9 ; NEXT(FALLTHRU)
0x1ba ; NEXT(FALLTHRU)
0x1bb ; NEXT(FALLTHRU)
0x1bc ; NEXT(FALLTHRU)
0x1bd ; NEXT(FALLTHRU)
0x1be ; NEXT(FALLTHRU)
0x1bf ; NEXT(FALLTHRU)
0x1c0 ; NEXT(FALLTHRU)
0x1c1 ; NEXT(FALLTHRU)
0x1c2 ; NEXT(FALLTHRU)
0x1c3 ; NEXT(FALLTHRU)
0x1c4 Syscall ; NEXT(FALLTHRU)
0x1c5 ; NEXT(FALLTHRU)
0x1c6 Ldcode16 ; NEXT(FALLTHRU)
0x1c7 ; NEXT(FALLTHRU)
0x1c8 ; NEXT(FALLTHRU)
0x1c9 Ldcode8 ; NEXT(FALLTHRU)
0x1ca ; NEXT(FALLTHRU)
0x1cb Stcode8 ; NEXT(FALLTHRU)
0x1cc Stcodelo ; NEXT(FALLTHRU)
0x1cd Stcode16 ; NEXT(FALLTHRU)
0x1ce ; NEXT(FALLTHRU)
0x1cf DMA_show ; NEXT(FALLTHRU)
0x1d0 ; NEXT(FALLTHRU)
0x1d1 ; NEXT(FALLTHRU)
0x1d2 ; NEXT(FALLTHRU)
0x1d3 ; NEXT(FALLTHRU)
0x1d4 ; NEXT(FALLTHRU)
0x1d5 ; NEXT(FALLTHRU)
0x1d6 ; NEXT(FALLTHRU)
0x1d7 ; NEXT(FALLTHRU)
0x1d8 ; NEXT(FALLTHRU)
0x1d9 ; NEXT(FALLTHRU)
0x1da Wdpte ; NEXT(FALLTHRU)
0x1db Shlb16 ; NEXT(FALLTHRU)
0x1dc Shla16 ; NEXT(FALLTHRU)
0x1dd Aluop16_16 ; NEXT(FALLTHRU)
0x1de Cmpb16_16 ; NEXT(FALLTHRU)
0x1df Cmp16_16 ; NEXT(FALLTHRU)
0x1e0 FltCnt ; NEXT(FALLTHRU)
0x1e1 ; NEXT(FALLTHRU)
0x1e2 ; NEXT(FALLTHRU)
0x1e3 ; NEXT(FALLTHRU)
0x1e4 PCtoMAR ; NEXT(FALLTHRU)
0x1e5 CopyMSWA ; NEXT(FALLTHRU)
0x1e6 Vshl ; NEXT(FALLTHRU)
0x1e7   ; NEXT(FALLTHRU)
0x1e8   ; NEXT(FALLTHRU)
0x1e9   ; NEXT(FALLTHRU)
0x1ea   ; NEXT(Fetch)
0x1eb Error ; NEXT(Error)
0x1ec   ; NEXT(FALLTHRU)
0x1ed ; NEXT(FALLTHRU)
0x1ee ; NEXT(FALLTHRU)
0x1ef ; NEXT(FALLTHRU)
0x1f0 LeaPC ; NEXT(FALLTHRU)
0x1f1 ; NEXT(FALLTHRU)
0x1f2 ; NEXT(FALLTHRU)
0x1f3 ; NEXT(LeaPC)
0x1f4 ; NEXT(FALLTHRU)
0x1f5 ; NEXT(FALLTHRU)
0x1f6 ; NEXT(FALLTHRU)
0x1f7 ; NEXT(FALLTHRU)
0x1f8 ; NEXT(FALLTHRU)
0x1f9 ; NEXT(FALLTHRU)
0x1fa ; NEXT(FALLTHRU)
0x1fb ; NEXT(FALLTHRU)
0x1fc ; NEXT(FALLTHRU)
0x1fd ; NEXT(FALLTHRU)
0x1fe Unreachable ; NEXT(FALLTHRU)
0x1ff UNUSABLE ; NEXT(FALLTHRU)

// ENDPREPROCESS prombits.h

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